In recent years, CPUs (central processing units) used for data processing apparatuses have become higher in operating frequency and remarkably increased in current consumption due to the improvement in processing speeds and higher integration. Along with this, there is a trend toward reduction of the power consumption so as to reduce the operating voltage. Therefore, in power sources for supplying power to CPUs, faster and larger current fluctuations occur. It has become extremely difficult to keep voltage fluctuations accompanying current fluctuations to within tolerances of the power sources.
Therefore, as shown in FIG. 12, a multilayer capacitor 100 called a “decoupling capacitor” is connected to a power source 102 and frequently used for stabilization of the power source. Further, by fast charging and discharging at the time of high speed, transient fluctuations in current, the multilayer capacitor 100 supplies current to the CPU 104 and suppresses voltage fluctuations in the power source 102.
Conventional multilayer capacitors are disclosed in for example Japanese Patent Unexamined Publication No. 2002-164256, Japanese Patent Unexamined Publication No. 2002-151349, Japanese Patent Unexamined Publication No. 2000-323354, Japanese Patent Unexamined Publication No. 11-144996, Japanese Patent Unexamined Publication No. 08-097070, and Japanese Patent Unexamined Publication No. 06-140283.
Along with the increasingly higher operating frequencies of today's CPUs, however, the current fluctuations have become faster and larger. Therefore, the equivalent serial inductance (ESL) of the multilayer capacitor 100 itself shown in FIG. 12 becomes relatively larger. Along with this, the effective inductance becomes larger. As a result, the equivalent serial inductance greatly influences voltage fluctuations of the power source.
That is, in a conventional multilayer capacitor used for the power source circuit of the CPU 104 shown in FIG. 12, since the ESL of the parasitic part shown in the equivalent circuit of FIG. 12 is high, along with fluctuations of the current I shown in FIG. 13, the ESL inhibits the charging and discharging of the multilayer capacitor 100. Therefore, in the same way as the above, the fluctuations in the voltage V of the power source easily become greater as shown in FIG. 13. Therefore, it will become impossible to handle the increasingly higher speeds of CPUs in the future.
This is because the voltage fluctuations at the time of transition of the current are approximated by the following equation 1 and therefore the level of the ESL is related to the magnitude of fluctuation of the power source voltage:dV=ESL·di/dt  formula (1)
Here, dV is transitory fluctuation of voltage (V), “i” is the amount of current fluctuation (A), and “t” is the time of fluctuation (sec).
Here, the appearance of this conventional capacitor is shown in FIG. 14, while the internal structure is shown in FIG. 15. Below, a conventional multilayer capacitor 100 will be explained based on these figures. That is, the conventional multilayer capacitor 100 shown in FIG. 14 is structured to give an electrostatic capacity by alternately stacking pairs of ceramic layers 112A each provided with two types of internal conductors 114 and 116 shown in FIG. 15 and forming a dielectric body 112.
Further, these two types of internal conductors 114 and 116 are led out to alternately facing two side surfaces 112B and 112C. Further, the terminal electrode 118 connected to the internal conductors 114 and the terminal electrode 120 connected to the internal conductors 116 are set at the alternately facing side surfaces 112B and 112C of the multilayer capacitor 100 shown in FIG. 14.
As shown in FIG. 16, the multilayer capacitor 100 is mounted with the ceramic layers 112A stacked along the perpendicular direction (Z-direction) with respect to the surface of a multilayer board 122, so the surfaces of the internal conductors 114 and 116 become horizontal with respect to the surface of the multilayer board 122. Therefore, the distance from the land patterns 124 of the conductor parts of the multilayer board 122 to the internal conductors 114 and 116 in the dielectric body 112 becomes longer and the area occupied by the current loop E becomes larger. As a result, in the conventional structure, there is the defect that the total inductance increases and along with this the effective inductance also ends up increasing.
In this way, as factors causing an increase in the voltage fluctuations of the power source, there are not only the ESL of the capacitor itself, but also the total inductance. The sum of the ESL and the total inductance has a great effect on the voltage fluctuations of the power source as the effective inductance. Therefore, it is necessary to reduce this effective inductance.
On the other hand, the structure shown in FIG. 17 may be considered as a mounting structure for avoiding an increase in the total inductance. In the mounting structure shown in the figure, the stacking direction of the internal conductors is made 90 degrees different from the structure shown in FIG. 16 and the ceramic layers 112A are stacked in the Y-direction along the surface of the multilayer board 122.
That is, the surfaces of the internal conductors 114 and 116 are perpendicular to the surface of the multilayer board 122 on which the multilayer capacitor 100 is mounted. Along with this, the current loop E becomes shorter. As a result, the total inductance is reduced.
However, no matter which structure is used, in the past, the total inductance could not be sufficiently reduced and it was not possible to eliminate the defect of the large effective inductance.